Basic Information


Course Description

SD01331440 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design, cache and virtual memory organizations, I/O and interrupts, scalar architectures and pipelining, vector supercomputers, and multiprocessor systems.

This course consists of three parts: lectures, assignments and experiments. The grades will be based on the students' performance on assignments and experiments (20%), as well as final exam (80%).

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Calendar

Course Period (Weeks) Type
Thu 3-4 1st-16th Lecture (N108)
Fri 7-8 1th-8th Lecture (N115)
Fri 7-8 9st-16th Lab

Slides

  • Introduction[PDF]
  • Fundamental Concepts[PDF]
  • Instruction Systems [PDF]
  • Memory Architecture [PDF]
  • I/O Systems [PDF]
  • Scalar Architectures[PDF]
  • Vector Supercomputers[PDF]
  • Internetwork[PDF]
  • Multiprocessor Systems[PDF]

Labs

A detailed report for each lab exercise is required. The technical report should be in pdf format and named as follows "Student ID_Name_Lab Index.pdf". For example, for a student whose name is 李雷 with student ID being 123456, his technical report for the 4th lab exercise should be "123456_李雷_实验1.pdf". Follows are some required materials for the lab exercises:

Lab exercises are scheduled as follows:

  • Exp 1 Familiarized with WinDLX [Due Date: Due Date: May 10, 2024]
  • Exp 2 Calculating the maximum common divisors [Due Date: May 17, 2024]
  • Exp 3 Calculating prime numbers [Due Date: Due Date: May 24, 2024]
  • Exp 4 Structural hazard [Due Date: May 31, 2024]
  • Exp 5 Data hazard [Due Date: June 7, 2023]
  • Exp 6 Instruction scheduling [Due Date: June 14, 2024]

Assignments

  • Problem Set 1[PDF] [Due Date: April 22, 2024]
  • Problem Set 2[PDF] [Due Date: May 6, 2024]
  • Problem Set 3[PDF] [Due Date: May 20, 2024]
  • Problem Set 4[PDF] [Due Date: June 3, 2024]

Tutorials


Useful Links

  • Some tips for Exp 4[PDF]